Multiple-Input Multiple-Output (“MIMO”) communication systems are becoming increasingly popular as a solution to increasing demands for higher data-rates and more reliable wireless communication systems. These systems comprise multiple antennas at a transmitter side of the communication system and multiple antennas at the receiver side of the communication system. Each transmitter antenna can transmit a different signal at a common frequency through a different channel of the communication system. Each receiver antenna may receive each signal from the multiple transmitter-antennas. During transit, the transmitted signals may encounter different obstacles such that the frequency response of each channel is different. Thus, a common goal of conventional systems is to attempt to efficiently detect the transmitted symbols by determining the frequency response of each channel in the communication system.
Although the optimal solution to the MIMO symbol detection problem, Maximum Likelihood (“ML”) detection, is known, a brute-force ML detector implementation involves an exhaustive search over all possible transmitted symbol vectors. This approach is infeasible for hardware implementations when either a large signal constellation or a large number of transmit and receive antennas are employed. Hence, a goal of conventional systems is to design hardware for MIMO symbol detection that achieves comparable Bit-Error-Rate (“BER”) performance to the ML detector while having low hardware complexity and meeting throughput and latency requirements.
Some conventional MIMO symbol detections systems employ methods of linear detection and Successive Interference Cancelation (“SIC”). Because most of the required processing for these detectors need only occur at the maximum packet-rate (preprocessing) and the required symbol-rate processing has relatively low-complexity, the throughput requirements for certain wireless standards, such as 802.11n, can be achieved in these systems. These methods, however, do not collect the same diversity (negative logarithmic asymptotic slope of the BER versus Signal-to-Noise-Ratio (“SNR”) curve) as ML detection. As a result, these methods exhibit greatly reduced system performance compared to ML detectors
Other conventional symbol detection systems employ Sphere Decoding (“SD”) algorithms. Hardware implementations of SD algorithms can achieve ML or near-ML performance. Unfortunately, these methods exhibit greatly increased symbol-rate processing complexity compared to linear or SIC detectors. The complexity of SD methods can also vary widely with changing channel conditions.
The maximum packet-rate of 802.11n is considerably less than the symbol-rate. Therefore, it is desirable to obtain detection systems and methods that achieve ML or near-ML performance at the cost of increased preprocessing complexity as opposed to increased symbol-rate processing complexity. Systems having these desired characteristics include Lattice Reduction (“LR”) aided detectors, which, unlike SD methods, incorporate LR algorithms into the preprocessing part of linear or SIC detectors and only increase the symbol-rate processing complexity slightly. Specifically, LR systems and methods only require lattice reduction once per received packet (per subcarrier). LR-aided detectors also exhibit the desirable property of having a complexity that is independent of both the channel SNR and signal constellation (assuming individual arithmetic operations have O(1) complexity).
A variety of hardware realizations of LR-aided detectors have been explored to exploit these properties and to achieve near-ML performance. Various explorations have included a VLSI implementation of a simplified Brun's LR algorithm and a software implementation of Seysen's LR algorithm on a reconfigurable baseband processor. Frequently explored variants, however, employ the Complex Lenstra-Lenstra-Lovász (“CLLL”) LR algorithm.
The CLLL algorithm has the desirable properties of requiring sorted QR-decomposition preprocessing instead of Direct Matrix Inversion (“DMI”) preprocessing. Further, the CLLL algorithm has superior performance to the conventional MIMO detection systems and does not suffer from the scalability issues in some of the conventional systems. The CLLL algorithm can also be used to significantly reduce the complexity of SD algorithms. The conventional CLLL algorithm, however, is unable to be feasibly implemented in fixed-point hardware architecture. Thus, given the desirable properties of the CLLL algorithm, the focus of the majority of LR-aided detection research has been on either improving BER performance or decreasing the complexity of CLLL-aided algorithms. Accordingly, the inventors of the present invention set forth a novel LR-aided detection process—a CLLL-Minimum Mean Square Error (“MMSE”)-SIC method—in U.S. patent application Ser. No. 12/943,824 entitled “Systems and Methods for Lattice Reduction,” which is incorporated herein by reference in its entirety as if fully set forth below.
A problem with conventional LR-aided detection processes arises from the iterative steps they employ. These processes often continually iterate through complex computational algorithms creating high costs in processing power and time. Therefore, there is a desire for more efficient and less complex LR-aided detection systems and methods. Various embodiments of the present invention address these desires.